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datasheet 9zxl1251 revision b 11/20/15 1 ?2015 integrated device technology, inc. 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 general description the 9zxl1251 meets the demanding requirements of the intel db1200zl specification, in cluding the critical low-drift requirements of in tel cpus. it is pin compatible to the 9zxl1231 and integrates 24 te rmination resistors, saving 41mm 2 board area. recommended application buffer for romley, grantley and purley servers, solid state storage and pcie output features ? 12 lp-hcsl output pairs w/integrated terminations (zo = 85 ? ) key specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew <50ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter <1.0ps rms ? phase jitter: qpi/upi >=9.6gb/s <0.2ps rms features/benefits ? 85 ? low-power push-pull hcsl outputs; eliminate 24 resistors, save 41mm 2 of area ? pin compatible to 9zx21201 and 9zxl1231; easy path to power and area savings ? space-saving 64-pin vfqfpn package ? fixed feedback path for 0ps input-to-output delay ? 9 selectable smbus addresse s; multiple devices can share the same smbus segment ? 12 oe# pins; hardware control of each output ? pll or bypass mode; supports common and separate clock architectures ? selectable pll bandwidth; mi nimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi ? -40c to +85c device available; supports demanding environmental applications block diagram logic dif(11:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) dfb_out_nc dif_in dif_in# oe(11:0)#
12-output db1200zl derivative with integrated 85 ? terminations 2 revision b 11/20/15 9zxl1251 datasheet pin configuration power management table functionality at power-up (pll mode) power connections dif_11# dif_11 voe11# voe10# dif_10# dif_10 gnd vdd vddio dif_9# dif_9 voe9# voe8# dif_8# dif_8 vddio 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vdda 1 48 gnd gnda 2 47 dif_7# nc 3 46 dif_7 ^100m_133m# 4 45 vo e 7 # ^vhibw_bypm_lobw# 5 44 vo e 6 # ckpwrgd_pd# 6 43 dif_6# gnd 7 42 dif_6 vddr 8 41 gnd dif_in 9 40 vdd dif_in# 10 39 dif_5# vs m b _a 0_t ri 11 38 dif_5 smbdat 12 37 vo e 5 # smbclk 13 36 vo e 4 # vs m b _a 1_t ri 14 35 dif_4# dfb_out_nc# 15 34 dif_4 dfb_out_nc 16 33 gnd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dif_0 dif_0# voe0# voe1# dif_1 dif_1# gnd vdd vddio dif_2 dif_2# voe2# voe3# dif_3 dif_3# vddio note: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldowm pins with ^v prefix have internal 120k pullup/pulldown (biased to vdd/2) 9zxl1251 connect epad (pin 65) to ground 9 x 9mm vfqfpn package ckpwrgd_pd# dif_in/ dif_in# smbus en bit dif(11:0)/ dif(11:0)# pll state if not in bypass mode 0 x x low/low off 0 low/low on 1 running on running 1 100m_133m# dif_in mhz dif(11:0) 1 100.00 dif_in 0 133.33 dif_in vdd vddio gnd 12 analo g pll 8 7 analog input 24,40,57 25,32,49,56 23,33,41,48, 58,65 dif clocks pin number description
revision b 11/20/15 3 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet pll operating mode readback table pll operating mode 9zxl1251 smbus addressing hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode smb_a1_tri smb_a0_tri smbus address 0 0 d8 0m da 0 1 de m0 c2 m m c4 m 1 c6 1 0 ca 1 m cc 11 ce pin
12-output db1200zl derivative with integrated 85 ? terminations 4 revision b 11/20/15 9zxl1251 datasheet pin descriptions pin # pin name type description 1 vdda pwr power for the pll core. 2 gnda gnd ground pin for the pll core. 3 nc n/a no connection. 4 ^100m_133m# in 3.3v input to select operating frequency. this pin has an internal pull-up resistor. see functionality table for definition 5 ^vhibw_bypm_lobw# latched in trilevel input to select high bw, bypass or low bw mode. this pin is biased to vdd/2 (bypass mode) with internal pull up/pull down resistors. see pll operating mode table for 6ckpwrgd_pd# in 3.3v input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 7 gnd gnd ground pin. 8vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 9 dif_in in hcsl true input 10 dif_in# in hcsl complementary input 11 vsmb_a0_tri in smbus address bit. this is a tri-level input that works in conjunction with the smb_a1 to decode 1 of 9 smbus addresses. it has an internal 120kohm pull down resistor. 12 smbdat i/o data pin of smbus circuitry, 5v tolerant 13 smbclk in clock pin of smbus circuitry, 5v tolerant 14 vsmb_a1_tri in smbus address bit. this is a tri-level input that works in conjunction with the smb_a0 to decode 1 of 9 smbus addresses. it has an internal 120kohm pull down resistor. 15 dfb_out_nc# out complementary half of differential feedback output, provides feedback signal to the pll for synchronization with input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the package. 16 dfb_out_nc out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the package. 17 dif_0 out hcsl true clock output 18 dif_0# out hcsl complementary clock output 19 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 20 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 21 dif_1 out hcsl true clock output 22 dif_1# out hcsl complementary clock output 23 gnd gnd ground pin. 24 vdd pwr power supply, nominal 3.3v 25 vddio pwr power supply for differential outputs 26 dif_2 out hcsl true clock output 27 dif_2# out hcsl complementary clock output 28 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 dif_3 out hcsl true clock output 31 dif_3# out hcsl complementary clock output 32 vddio pwr power supply for differential outputs 33 gnd gnd ground pin. 34 dif_4 out hcsl true clock output 35 dif_4# out hcsl complementary clock output 36 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 37 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs
revision b 11/20/15 5 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet pin descriptions (cont.) pin # pin name type description 38 dif_5 out hcsl true clock output 39 dif_5# out hcsl complementary clock output 40 vdd pwr power supply, nominal 3.3v 41 gnd gnd ground pin. 42 dif_6 out hcsl true clock output 43 dif_6# out hcsl complementary clock output 44 voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 45 voe7# in active low input for enabling dif pair 7. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 46 dif_7 out hcsl true clock output 47 dif_7# out hcsl complementary clock output 48 gnd gnd ground pin. 49 vddio pwr power supply for differential outputs 50 dif_8 out hcsl true clock output 51 dif_8# out hcsl complementary clock output 52 voe8# in active low input for enabling dif pair 8. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 53 voe9# in active low input for enabling dif pair 9. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 54 dif_9 out hcsl true clock output 55 dif_9# out hcsl complementary clock output 56 vddio pwr power supply for differential outputs 57 vdd pwr power supply, nominal 3.3v 58 gnd gnd ground pin. 59 dif_10 out hcsl true clock output 60 dif_10# out hcsl complementary clock output 61 voe10# in active low input for enabling dif pair 10. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 62 voe11# in active low input for enabling dif pair 11. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 63 dif_11 out hcsl true clock output 64 dif_11# out hcsl complementary clock output 65 epad gnd epad, connect to ground
12-output db1200zl derivative with integrated 85 ? terminations 6 revision b 11/20/15 9zxl1251 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9zxl1251. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaran teed only over the recommended operating temperature range. electrical characteristics?di f_in clock input parameters electrical characteristics?smbus parameter symbol conditions min typ max units notes supply voltage vddx 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v d d +0.5 v 1,3 input high voltage v ihsmb smbus clock and data pins 5.5 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 4.6v. t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input crossover voltage - dif_in v cross cross over voltage 150 900 mv 1 input swing - dif_in v swing differential value 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes smbus input low voltage v ilsmb 0.8 v smbus input high voltage v ihsmb 2.1 v ddsmb v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 2.7 3.6 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 5 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the smbus to be active 3 time from deassertion until out p uts are >200 mv 4 dif_in input
revision b 11/20/15 7 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet electrical characteristics?in put/supply/common parameters t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage, except vddio 3.135 3.3 3.465 v output supply voltage vddio supply voltage for dif outputs, if present 0.95 1.05 3.465 v commmercial range (t com )0 70c industrial range (t in d ) -40 85 c input high voltage v ih single-ended inputs, except smbus, tri-level inputs 2v dd + 0.3 v input low voltage v il single-ended inputs, except smbus, tri-level inputs gnd - 0.3 0.8 v input high voltage v ihtri tri-level inputs 2.2 v dd + 0.3 v input mid voltage v imtri tri-level inputs 1.2 vdd/2 1.8 v input low voltage v iltri tri-level inputs gnd - 0.3 0.8 v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua f ib yp v d d = 3.3 v, bypass mode 33 150 mhz f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.18 1.8 ms 1,2 input ss modulation frequency pcie f modinpci e allowable frequency for pcie applications (triangular modulation) 30 33 khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 10 clocks 1,2,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 2 trise t r rise time of control inputs 5 ns 2 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until out p uts are >200 mv 4 dif_in input ambient operating temperature t amb input current input frequency capacitance
12-output db1200zl derivative with integrated 85 ? terminations 8 revision b 11/20/15 9zxl1251 datasheet electrical characteristics?di f low power hcsl outputs electrical characteristi cs?current consumption t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes t amb = t com , scope averaging on 1.6 3.3 4 v/ns 1,2,3 t amb = t in d scope averaging on 1.6 2.8 4.1 v/ns 1,2,3 slew rate matchin g dv/dt slew rate matchin g , scope avera g in g on 7 20 % 1,2,4 voltage high vhigh 660 754 850 voltage low vlow -150 62 150 max volta g e vmax 868 1150 min volta g evmin -300-64 crossin g volta g e (abs) vcross_abs scope avera g in g off 250 453 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 17 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. slew rate dv/dt statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope avera g in g off) mv 1 guaranteed by desi g n and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes vdda, pll mode@100mhz 13.4 20 ma 1 vdda, pll bypass mode@100mhz 4.8 8 ma 1 i d d all other vdd pins 16 25 ma i ddi o vddio for dif outputs, if applicable 81 95 ma vdda, pll mode@100mhz 3 5 ma 1 vdda, pll bypass mode@100mhz 3 5 ma 1 i d d all other vdd pins 0.14 1 ma i ddi o vddio for dif outputs, if applicable 0.01 0.3 ma 1. includes vddr if applicable operating supply current i dda power down current i dda
revision b 11/20/15 9 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet electrical characteristics?skew and differential jitter parameters t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode @100mhz, nominal temperature and voltage -100 3 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode @100mhz, nominal temperature and volta g e 2.5 3.6 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode @100mhz, across voltage and temperature -50 0 50 ps 1,2,3,5,8 input-to-output skew varation in bypass mode @100mhz, across voltage and temperature, t amb = t com -250 250 ps 1,2,3,5,8 input-to-output skew varation in bypass mode @100mhz, across voltage and temperature, t amb = t ind -350 350 ps 1,2,3,5,8 output-to-output skew across all outputs @100mhz, t amb = t com 36 50 ps 1,2,3,8 output-to-output skew across all outputs @100mhz, t amb = t in d 38 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 0 1.2 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 0 0.8 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 234mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.1 1.4 mhz 8,9 duty cycle t dc measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1.5 -0.6 0 % 1,10 pll mode 25 50 ps 1,11 additive jitter in bypass mode 1 5 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band g ain. at frequencies within the loop bw, hi g hest point of ma g nification is called pll jitter peakin g . 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 11 measured from differential waveform 2 measured from differential cross-point to differential cross-point. this parameter can be tuned with external feedback path, if present. 10 duty cycle distortion is the difference in duty cycle between the output and the i nput clock when the device is operated in bypass mode. 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value. dif[x:0] t skew_all jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. clk_in, dif[x:0] t dspo_byp
12-output db1200zl derivative with integrated 85 ? terminations10 revision b 11/20/15 9zxl1251 datasheet electrical characteristics? phase jitter parameters t amb = t com or t ind , unless noted., supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max ind.limit units notes t jp hpcieg1 pcie gen 1 36 49 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 1.6 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.2 2.8 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.56 0.63 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.22 0.48 0.5 ps (rms) 1,4 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.15 0.28 0.3 ps (rms) 1,4 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.11 0.17 0.2 ps (rms) 1,4 t jp hpcieg1 pcie gen 1 0.0 0.8 n/a ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.2 n/a ps (rms) 1,2,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.4 0.5 n/a ps (rms) 1,2,5 t jphpcieg3 pcie gen 3 (pll bw of 2-4 or 2-5 mhz, cdr = 10mhz) 0.0 0.0 n/a ps (rms) 1,2,4,5 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.11 0.2 n/a ps (rms) 1,4,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.00 0.01 n/a ps (rms) 1,4,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.00 0.01 n/a ps (rms) 1,4,5 1 applies to all outputs. 5 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total ji ttter)^2 - (i nput jitter)^2] additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extr apolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 calculated from intel-supplied clock jitter tool v 1.6.3 phase jitter, pll mode t jphpcieg2 t jphqpi_smi
revision b 11/20/15 11 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 ssc off dif measurement wi ndow units notes center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven by cpu output of main clock, 133 mhz pll mode or bypass mode notes 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9zxl1251 itself does not contribute to ppm error. dif measurement window units ssc on center freq. mhz 85ohm differential zo low-power hcsl output buffer w/internal termination 2pf 2pf 10 inches differential output terminations dif zo ( ? )rs ( ? ) 100 na 85 0
12-output db1200zl derivative with integrated 85 ? terminations12 revision b 11/20/15 9zxl1251 datasheet general smbus serial interface information for 9zxl1251 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
revision b 11/20/15 13 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet smbustable: pll mode, and frequency select register pin # name control function t yp e0 1default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll b w r w hw latch smbus control 0 bit 2 pll mode 1 pll o p eratin g mode 1 r w 1 bit 1 pll mode 0 pll o p eratin g mode 1 r w 1 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e0 1default bit 7 dif_7_en out p ut control - '0' overrides oe# p in r w 1 bit 6 dif_6_en out p ut control - '0' overrides oe# p in r w 1 bit 5 dif_5_en out p ut control - '0' overrides oe# p in r w 1 bit 4 dif_4_en out p ut control - '0' overrides oe# p in r w 1 bit 3 dif_3_en out p ut control - '0' overrides oe# p in r w 1 bit 2 dif_2_en out p ut control - '0' overrides oe# p in r w 1 bit 1 dif_1_en out p ut control - '0' overrides oe# p in r w 1 bit 0 dif_0_en out p ut control - '0' overrides oe# p in r w 1 smbustable: output control register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 dif_11_en out p ut control - '0' overrides oe# p in r w 1 bit 2 dif_10_en out p ut control - '0' overrides oe# p in r w 1 bit 1 dif_9_en out p ut control - '0' overrides oe# p in r w 1 bit 0 dif_8_en out p ut control - '0' overrides oe# p in r w 1 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved low/low enable reserved reserved reserved reserved reserved b y te 4 b y te 2 b y te 3 4 b y te 1 26/27 21/22 17/18 43/42 39/38 50/51 64/63 b y te 0 5 5 47/46 59/60 35/34 30/31 54/55 see pll operating mode readback table low/low enable see pll operating mode readback table note: setting bit 3 to '1' allows the user to overide the latch value from pin 5 via use of bits 2 and 1. use the values from the pl l operating mode readback table. note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will h ave to accomplished if the user changes these bits. reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
12-output db1200zl derivative with integrated 85 ? terminations14 revision b 11/20/15 9zxl1251 datasheet smbustable: vendor & revision id register pin # name control function t yp e 0 1 default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e 0 1 default bit 7 r1 bit 6 r1 bit 5 r1 bit 4 r1 bit 3 r1 bit 2 r0 bit 1 r1 bit 0 r1 smbustable: byte count register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 r w 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 r w 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved device id 7 ( msb ) reserved device id 5 device id 6 reserved b y te 5 reserved - b y te 7 - - - - - device id 3 vendor id - - - b y te 6 - - - - - - - b y te 8 - - reserved device id 2 device id 1 device id 4 revision id a rev = 0000 - - - 1251 is 251 decimal or fb hex reserved reserved writing to this register configures how many bytes will be read back. default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. reserved device id 0 reserved reserved reserved
revision b 11/20/15 15 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet marking diagram notes: 1. ?i? denotes industrial temperature grade. 2. ?l? denotes rohs compliant package. 3. ?lot? denotes the lot number. 4. ?coo? denotes country of origin. 5. ?yyww? is the last two digits of the year and week that the part was assembled. ics 9zxl1251akl lot coo yyww ics 9zxl1251ail lot coo yyww
12-output db1200zl derivative with integrated 85 ? terminations16 revision b 11/20/15 9zxl1251 datasheet nlg64 package outline and package dimensions
revision b 11/20/15 17 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet nlg64 package outline and package dimensions, cont. use option 2 dimensions table .
12-output db1200zl derivative with integrated 85 ? terminations18 revision b 11/20/15 9zxl1251 datasheet nlg64 package outline and package dimensions, cont. use epad 6.15 option
revision b 11/20/15 19 12-output db1200zl derivative with integrated 85 ? terminations 9zxl1251 datasheet ordering information "lf" suffix to the part number denotes pb-free configuration, rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision). revision history part / order number shipping package package temperature 9zxl1251aklf trays 64-pin vfqfpn 0 to +70c 9zxl1251aklft tape and reel 64-pin vfqfpn 0 to +70c 9zxl1251akilf trays 64-pin vfqfpn -40 to +85c 9ZXL1251AKILFT tape and reel 64-pin vfqfpn -40 to +85c rev. issuer issue date description page # a rdw 7/23/2015 update to final and release various b rdw 11/20/2015 1. updated qpi references to qpi/upi 2. updated dif_in table to match pci sig specification, no silicon change 1,6
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